Program counters are used in data processing apparatus to indicate the address where an instruction to be executed is stored. In a processor generally an instruction is fetched, decoded and then executed. If the processor is pipelined, then at any one time there will be an instruction being fetched, another one being decoded and a further one being executed. Thus, at any one time there are generally multiple instructions at different places within the pipeline and multiple program counters can be used to identify the instructions in each part of the pipeline.
In some processors where it is desirable to reduce gate count, only one program counter is used to indicate an address of one of the instructions, say the instruction to be fetched, and the addresses of the other instructions within the processing path can be derived from this address and known delays, where consecutive instructions are being processed.
If there is a change in program flow, then one can no longer predict the address of an instruction currently being executed from an address of an instruction being fetched.
Following a change in program, flow due for example to an interrupt, the instruction address of the instruction currently being executed needs to be stored so that the program can return to the point at which it was interrupted. Conventionally software has been used to calculate from a single program counter and known delays what instruction is currently being executed. This is expensive in time and resources.
It would be desirable to be able to use a single program counter and to be able to determine both the address of an instruction at a certain point in the processing path and the address of an instruction to be fetched following a change in program flow, in a way that is power, time and area efficient.